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1 intel corporation order number: d55745-002 intel and the intel logo are registered trademarks of intel corporation or its subsidiaries in the united states and other coun tries. *other names and brands may be claimed as the property of others. copyright ? 2007 intel corporation. all rights reserved. features ? direct conversion tuner for quadrature down conversion from l-band to zero if ? symbol rate 1-45 ms/s ? high sensitivity < -83 dbm at 27.5 ms/s code rate 7/8 ? independent rf agc and baseband gain control ? fifth order baseband filters with bandwidth adjustable from 6 to 43 mhz ? fully integrated alignment-free low phase noise local oscillator ? selectable rf bypass ? low power consumption 0.5w at 3.3v. ? 28 pin 5x5 mm qfn package applications ? dvb-s paytv satellite receivers ? dss satellite receivers ? dvb-s2 8psk satellite receivers description the CE5037 is a fully integrated direct conversion tuner for digital satellite receiver systems. it provides excellent immunity to composite undesired channels. the device also contains a rf bypass for connecting to a second receiver module. the CE5037 is simple to use, requiring no alignment or tuning algorithms and uses a minimum number of external components. the device is programmable via a i 2 c compatible bus. the CE5037 is qualified for dvb-s2 8psk receiver applications a complete reference design (ce9542) is available using ce6313 demodulator. january 2007 ordering information wgCE5037 882557 28 pin qfn* trays wgCE5037 s l9fv 882558 28 pin qfn* tape & reel *pb free matte tin -10 c to +85 c CE5037 digital satellite tuner with rf bypass data sheet figure 1 - basic block diagram pll i 2 c control loop filter ce6313 CE5037 quadrature vco rf input bypass output i q crystal qpsk demodulator rf agc
CE5037 data sheet 2 intel corporation table of contents 1.0 circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 local oscillator generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.0 register map and programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 pll registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 rf control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 base band registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 local oscillator registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5 general control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.0 applications information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 general design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 dvb-s2 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 baseband filter bandwidth calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.0 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.0 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.0 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.0 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.0 typical performance data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
CE5037 data sheet 3 intel corporation figure 2 - pin diagram table 1 - pin names note: ground contact is via underside of package. pin 2 is connected to ground internally. pin # name description pi n # name description 1 vvar lo tuning voltage 15 qout q channel baseband output 2 pad/ref vvar reference ground / continuity test 16 qout q channel baseband output 3 vccvco vco supply 17 vccbb baseband supply 4 vcclo lo supply 18 iout i channel baseband output 5 lotest lo test pin - do not connect 19 iout i channel baseband output 6 rfbypass rf bypass output 20 sleep hardware power down input 7 vccrf2 rf supply 21 scl i 2 c clock 8 vccrf1 rf supply 22 sda i 2 c data 9 n/c not connected 23 p0 general purpose switching output 10 rfin rf input 24 xcap crystal oscillator feedback 11 n/c not connected 25 xtal crystal oscillator crystal input 12 rfin rf complementary input 26 vccdig digital supply 13 n/c not connected 27 vccc p varactor tuning supply 14 rfagc rf gain control input 28 pump pll charge pump output ground - package paddle CE5037 1 rfagc n/c rfin n/c rfin n/c vccrf1 vvar pad/ref vccvco vcclo lotest rfbypass vccrf2 scl sda p0 xcap xtal vccdig vcccp pump sleep iout iout vccbb qout qout
CE5037 data sheet 4 intel corporation figure 3 - detailed block diagram rfin 15 bit programmable divider charge pump i2c bus interface ref osc reference divider fcomp rfin sda scl xtal xcap pump iout qout rfagc phase splitter vco bank 0 deg p0 rfbypass filter filter bandwidth adjust lock detect dc correction vccdig vcccp vccbb vccfe1 vccfe2 vcclo qout iout lotest pad/ref (paddle) sleep dc correction vccvco vvar 10db switched gain (rfg) port interface fpd bf 90 deg
CE5037 data sheet 5 intel corporation 1.0 circuit description 1.1 functional description the CE5037 is a single chip wide band dire ct conversion tuner with in tegral rf bypass optimised for digital satellite receiver systems. it provides excellent signal handling capability in the pres ence of high composite signal levels. the device offers a highly integrated solution for a satellite tuner incorporating a low phase noise pll frequency synthesizer, the quadrature down conver ter, a fully integrated local osci llator, and programmable baseband channel filters. a minimal number of additional peripheral components are requir ed. the crystal reference source can be also used as the reference for the demodulator. an i 2 c compatible bus interface controls all of the tuner functionality. the CE5037 contains both hardware and software power down modes. 1.2 signal path 1.2.1 rf input the tuner rf input signal at a frequency of 950 ? 2150 mh z is fed to the CE5037 rf input pre-amplifier stage. the signal handling is designed such that no tracking filter is required to offer immuni ty to input signal composite overload. the rf input amplifier feeds an agc stage, which provides rf gain control. there is additional gain adjustment in the baseband section. t he total agc gain range will gu arantee an operating dynamic range of ?92 to ?10 dbm. the rf agc in the CE5037 is divided into two stages. t he first stage is a continually variable gain control stage, and provides the main system agc set under control of the analogue agc signal generated by the demodulator section. the second stage is a programmable gain stage to reduce rf gain by 10 db. this would normally be used when an external lna is being used to improve system sensitivity. the analogue rf agc is optimised for s/n and s/i perfo rmance across the full dynamic range. typical rf agc characteristic and variation of iip3, iip2 and nf ar e shown in section 8 - typical performance curves. the output of the agc stage is coupled to the quadrature mixer where the rf signal is mixed with quadrature local oscillator signals generated by the on-board local oscillator. 1.2.2 baseband the outputs of the quadrature down converter are passed through the baseband filters followed by a programmable baseband gain stage. the baseband paths are dc coupled. an integrated dc correction loop prevent s saturation due to local oscillator self-mixing in the converter section. no extern al components are required for dc correction. the baseband filters are 5 th order chebychev and provide excellent matching in both amplitude and phase between the i and q channels. the filt ers are fully programmable for 3 db bandwidths from 6 mhz to 43 mhz. the recommended filter bandwidth is related to the required symbol rate by the following equation. this equation makes no allowance for lnb tuning offset at low symbol rates < 10 ms/s. 8 . 0 2 35 . 1 3 = ? symbolrate fc width filterband db
CE5037 data sheet 6 intel corporation the baseband filter uses an automatic tuning algorithm to calibrate the filter bandwidth to the programmed requirement. this removes any variation due to operati ng conditions and process variat ions. the automatic tuning algorithm uses a frequency locked loop, which locks the filt er bandwidth to a reference frequency derived from the crystal reference input frequency. further details are provided in the programming section. the filters are followed by a programmable gain stage. this provides twelve 1.5 db gain steps. these can be used for optimising performance at different symbol rates and for adjusting the output leve l in applications not using ce6313. the differential outp uts of each channel stage ar e designed for low impedance drive capability and low intermodulation. the device can also be used in single-ended applications with unused outputs. 1.2.3 rf bypass the CE5037 provides a single ended bypass function, which can be used for driving a second receiver module. the electrical characteristics of the rf input are unchanged whether the rf bypass is enabled or disabled. the rf bypass powers up in the enabled state and can also operate with the remainder of the device in power down modes. 1.3 local os cillator generation 1.3.1 on chip vco the local oscillator on the CE5037 is fu lly integrated. it consists of three independently se lectable oscillator stages with sub bands. the three o scillators and sub-bands are designed to provide optim um phase noise performance over the required tuning ra nge of 950 to 2150 mhz, over operat ing conditions and process variations. the local oscillators operate at a harm onic of the required local oscillator frequency and are divided down to the required lo frequency. th e required divider rati o is automatically sele cted by the local o scillator control logic. the oscillators are fully controlled by an on-chip automat ic tuning algorithm. the user simply programs the required lo frequency. the control logic automatically sele cts the required vco and sub band to give optimum performance. vco settling time is minimized as differ ent tuning algorithms are us ed, depending on the magnitude of the lo frequency change required. th is choice of algorithm is also automatic and does not require user intervention. the oscillator control logic tracks any ch anges in operating condit ions and will retune the vco if necessary, however hysteresis is built into this function to avoid unnecessary switching. all oscillator components are included on the chip including the vco varactor. an external loop filter is required as part of the pll frequency synthesizer. 1.3.2 pll fre quency synthesizer the fully integrated pll frequency synthesizer section c ontrols the lo frequency. the only external requirements are crystal reference and simple sec ond order loop filter. the pll can be op erated up to comparison frequencies of 2 mhz enabling a wide loop bandwidth for maximizing the close in phase noise performance. the local oscillator input signal is multiplexed from the ac tive oscillator to an internal preamplifier, which provides gain and reverse isolation from the divi der signals. the output of the preamplifie r provides the input to a 15-bit fully programmable divider with mn+a architecture incorporating a dual modulus 16/17 prescaler. the output of the programm able divider is fed to the phase comparat or where it is compared in both phase and frequency domain with the comparison frequency. this fr equency is derived either from the on-board crystal controlled oscillator or from an external reference source. in both cases the referenc e frequency is divided down to the comparison frequency by the re ference divider, which is programmable into 1 of 15 ratios.
CE5037 data sheet 7 intel corporation the output of the phase detector feeds a charge pump whic h combined with an external lo op filter integrates the current pulses to control the varactor voltage. the charge pump current is automatically varied by the vco control logic to compensate for vco gain vari ations that are dependent on selected s ub band. the varactor control voltage is externally coupled to the oscillat or section through t he input pin vvar. 1.4 i 2 c interface all programming for the CE5037 is controlled by an i 2 c data bus and is compatible with 3v3 standard mode formats. data and clock are fed in on the sda and sc l lines respectively as defined by i 2 c bus format. the device can either accept data (write mo de), or send data (read mode). the lsb of t he address byte (r/w) sets the device into write mode if it is logic ?0?, and read mode if it is logic ?1?. the i 2 c address is fixed at c0 (write)/c1(read) in hex format. the CE5037 contains 16 control registers. these register s are read/write registers. t hese registers are addressed as sub-addresses on the i 2 c bus. registers can be addressed as rando m access single write/read or random access sequential write and read as shown below. random access single write random access sequential write stop random access single read random access sequential read w write bit a acknowledge bit n not acknowledge a sleep pin is provided. this powers down all sections of the chip including the crystal oscillator and i 2 c interface. the rf bypass function will be operational in this mo de providing it has been previously enabled through the i 2 c interface. stop start device address w a register address n a register data n a stop stop start device address w a register address n a register data n a register data n+1 ... register data n+m a stop stop start device address w a register address n a start device address r a register data n n stop stop start device address w a register address n a start device address r a register data n a ... register data n+m n stop
CE5037 data sheet 8 intel corporation 2.0 register map and programming the register map is arranged as 16 by te-wide read/write registers grouped by functional block. the registers may be written to and read-back from either sequentially (for lowest overhead) or s pecifically (for maximum flexibility). a significant number of bits are used for test and evaluat ion purposes only and are fix ed at logic ?0? or ?1?. the correct programming for these test bits is shown in the table below. it is essential that these values are programmed for correct operation. when the content s of the registers are read back the value of some bits may have changed from their programmed value. this is due to the internal automatic control which can update registers. any changes can be ignored. read only bits are marked with an asterisk (*). any data written to these bits will be ignored. registers are set to default settings on applying power. these conditions are shown below and in the applicable tables. x* denotes a read only test bit register block function 0pll plf2 14 2 13 2 12 2 11 2 10 2 9 2 8 1pll 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 pll 0 0 c1 c0 r3 r2 r1 r0 3 pll x*1000000 4 rf front end x*11011lenrfg 5 base band bf7 bf6 bf5 bf4 bf3 bf2 bf1 bf0 6 base band 0 lf sf br4 br3 br2 br1 br0 7 base band blf* bg3 bg2 bg1 bg0 0 0 0 8 local oscillator flf*0100000 9 local oscillator 10100010 a local oscillator 11110001 b local oscillator x*x*111000 c local oscillator 11010000 d local oscillator x* x* x* 1 0 0 0 0 e local oscillator x*x*110000 f general pd clr p0 0 x* x* x* x* table 2 - register map
CE5037 data sheet 9 intel corporation 2.1 pll registers there are four register s that control the pll: the plf bit is the pll lock detect circuit output. the plf bi t is set after 64 consecutive comparison cycles in lock. a chip-wide reset initializes the lock detect output to 0. the 2[ 14:8 ] bits are the msb bits of the lo divider divide value. the 2[ 7:0 ] bits are the lsb bits of the lo divider divide value. the division ratio of the lo divider is fully programmable to integer values within the range of 240 to 32767. note that when the lo divider divide value is to be changed, the new val ue is not actually presented to the lo divider until all of the 15-bit control word 2[ 14:0 ] has been programmed. register 0 and 1 must be therefore be programmed (in any order) before the lo divider is updated even if the only data change is in one of the registers. the c[1:0] bits set the programmed charge pump current . the charge pump current is automatica lly increased to the next setting de pendent on the vco sub band that has been selected by the vco tuning algorithm. this is to compensate for changes in vco gain and so provide consistent pll performance across all sub bands. progra mming the highest charge pump value will not allow the value to be incremented, therefore this value should not be programmed. the value read back for the charge pump current is the actual value in use for the selected sub band. bit field name default type description 7 plf - r pll lock flag 6:0 2 [14:8] 0 r/w msb bits of lo divider register table 3 - register 0 bit field name default type description 7:0 2 [7:0] 0 r/w lsb bits of lo divider register table 4 - register 1 bit field name default type description 7:6 - 0 r/w test modes 5:4 c[1:0] 0 r/w charge pump current 3:0 r[3:0] 0 r/w reference divider ratio table 5 - register 2 c[1] c[0] typ units 0 0 400 ua 0 1 550 ua 1 0 750 ua 1 1 1000 ua table 6 - charge pump currents
CE5037 data sheet 10 intel corporation the r[3:0] bits select the reference divider divide ratio. the ratio selected is not a simple binary power-of-two value but through a lookup table, see ta ble 7- pll reference divider ratios. this register controls test modes within the pll. this should be programmed with the default settings. 2.2 rf control register a single register contro ls rf programmability. r3 r2 r1 r0 division ratio 00002 00014 00108 001116 010032 01 0164 0110128 0111256 10003 10015 101010 101120 110040 11 0180 1110160 1111320 table 7 - pll reference divider ratios bit field name default type description 7:0 - 0x40 r/w test modes table 8 - register 3 bit field name default type description 7 - - r test modes 6:2 - 11011 r/w test modes 1 len 1 r/w bypass enable 0 rfg 0 r/w rf gain adjust table 9 - register 4
CE5037 data sheet 11 intel corporation the len bit enables the rfbypass output. with this bit se t, the rf bypass is active even if ?software? or ?hardware? power down has been selected. the rfg bit controls the gain of the se cond section of rf gain control. with this bit set, the rf gain is reduced by 10db. this setting would normally used when an external lna is being used. 2.3 base band registers there are three registers that control the base band: the bits bf[7:0] control the bandwidth of the baseband f ilter. an automatic adjustment routine synchronizes the filter bandwidth to a reference frequency derived from the crystal. the lf and sf bits disable the baseband filter adjustmen t. it is recommended that these bits are set after programming the filter bandwidth to prev ent interactions within the circuit. t hese bits must be reset to enable the baseband filter bandwidth to be reprogrammed. the br[4:0] bits set the crystal reference divide ratio. this effectively determines the resolution setting of the baseband filters. the baseband filter settings (b f[7:0]) can be calculated fr om the following equation. see section 3 applications informati on, for a typical programming example. br[4:0] = 0 is invalid the blf bit indicates that the baseb and adjustment has completed and locked. the control bits bg[3:0] define the gain of the base band post-filter amplifier. the following table shows the gain - note this is relative gain. the 1.5 db gain steps enab le the baseband output level to be adjusted and optimise gain distribution for different symbol rates. bit field name default type description 7:0 bf[7:0] 0x3c r/w base band filter cut-off frequency table 10 - register 5 bit field name default type description 7-0r/wtest mode 6 lf 0 r/w baseband filter adjust disable 5 sf 0 r/w baseband filter adjust disable 4:0 br[4:0] 1000 r/w base band reference division ratio table 11 - register 6 bit field name default type description 7 blf - r base band lock flag 6:3 bg[3:0] 0111 r/w base band gain select 2:0 - 000 r/w test modes table 12 - register 7 1 ( ? = (mhz) frequency crystal 0]) : br[4 * 5.088 * (mhz) bandwidth filter 0] : bf[7
CE5037 data sheet 12 intel corporation 2.4 local oscillator registers there are seven registers that control the local oscillator: these are us ed primarily for test and evaluation by intel corporation. although vco?s can be manually programmed, the user is recommended to use the default automatic settings as these prov ide optimum performance. the flf bit is the vco tuning controller lock output and is set when pll is locked and the automatic vco tuning is optimised and complete. register 9 to register e are for test modes only. it is however important that thes e registers are programmed with the values shown. bg[3] bg[2] bg[1] bg[0] gain (db) 00000 00011.5 00103.0 00114.5 01006.0 01017.5 01109.0 011110.5 100012.0 100113.5 101015.0 101116.5 table 13 - bg[3:0] control of base band post filter gain bit field name default type description 7 flf - r full lock flag 6:0 - 0x20 r/w test modes table 14 - register 8
CE5037 data sheet 13 intel corporation bit field name default type description 7:0 - 0xa2 r/w test modes table 15 - register 9 bit field name default type description 7:0 - 0xf1 r/w test modes table 16 - register a bit field name default type description 7:6 - - r test modes (read only) 5:0 - 0x38 r/w test modes table 17 - register b bit field name default type description 7:0 - 0xd0 r/w test modes table 18 - register c bit field name default type description 7:5 - - r test modes (read only) 4:0 - 0x10 r/w test modes table 19 - register d bit field name default type description 7:6 - - r test modes (read only) 5:0 - 0x30 r/w test modes table 20 - register e
CE5037 data sheet 14 intel corporation 2.5 general control register this register controls powerdown and general control functions: the pd bit is the ?software? power down control. when this bit is set to 1, all the analogue blocks are powered down with the exception of the crystal oscillator. the i 2 c interface will remain active and can still be used to enable the rf bypass. setting the sleep input pin high also invokes ?software? pow er down with the addition of powering down the crystal oscillator to produce ?hardware? power down. the rf bypass will remain active if it has been previously programmed on the i 2 c bus. note that in ?hardware? power down, the i 2 c interface does not operate. the clr bit re-triggers the power-on-reset function. this resets all register va lues to their power-on reset default value. the clr bit is itself cleared. note that the chip-wide reset will reset the i 2 c interface and the current write sequence used to set this bit will not be acknowledged. the p0 bit controls the state of the output port according to table 22. bit field name default type description 7 pd 1 r/w power down 6 clr 0 r/w clear and reset logic 5 p0 0 r/w port 0 control 4-0r/wtest mode 3:0 - - r test modes (read only) table 21 - register f p0 output port state 0 off, high impedance 1 on, current sinking table 22 - output port states
CE5037 data sheet 15 intel corporation 3.0 applications information figure 4 - typical application with ce6313 demodulator c25 10nf +3v3_d c27 10nf c29 10nf c26 10nf c30 10nf mdo0 mdo1 mdo2 mdo3 mdo4 mdo5 mdo6 mdo7 moclk status diseqc0 diseqc1 bkerr moval mostrt irq vcor e +3v3_d r9 100k diseqc1 3 diseqc0 4 reset 1 status 64 clk1 10 data1 11 irq 43 mostrt 46 moclk 62 mdo0 48 mdo1 49 mdo2 52 mdo3 53 mdo4 56 mdo5 57 mdo6 60 mdo7 61 moval 47 bkerr 63 vd d 5 addr4 38 addr3 37 addr2 36 addr1 35 cvd d 17 gnd 18 gnd 26 sleep 9 i in 25 i in 24 cvd d 32 gnd 31 q in 30 q in 29 gnd 23 cvd d 22 gnd 28 agc 41 xti 19 xto 20 vd d 39 clk2 15 data2 14 diseqc2 2 cvd d 7 cvd d 12 cvd d 50 cvd d 44 vd d 27 cvd d 59 vd d 55 gnd 21 gnd 58 gnd 54 gnd 51 gnd 45 gnd 40 gnd 13 gnd 8 gnd 6 oscmode 16 cvd d 34 gnd 33 te st 42 anal og ue digital a n al o g ue digital digital u1 ce6313 diseqc2 data1 clk1 sleep r11 22k r10 36k +3v3_d data2 clk2 r16 4k7 r17 4k7 +3v3_d +3v3_d reset +3v3_d x1 10.111mhz c31 100nf +3v3_d c32 100nf c36 100nf c33 100nf c34 100nf vcore c37 100nf c38 100nf c39 100nf c40 100nf c41 100nf c42 100nf c43 100nf c44 100nf c28 100nf c35 100nf c47 220nf r25 100r r24 1k2 tp17 r23 1k +3v3_d r14 100r r15 100r tp12 tp11 r8 470r r20 51r c48 22pf c51 nf r19 51r c21 22pf c45 nf r18 51r c17 22pf c18 nf r6 51r c1 22pf c2 nf c14 100nf r5 100k c12 10pf c13 10pf sl eep c11 47pf c3 56pf c4 56pf c5 10nf c10 220nf +3v3_a xtal d1 bar63-03w c23 10nf c57 100pf c46 220nf l3 blm18rk102sn1d c6 10nf c7 220pf c9 22pf r3 8k2 r2 8k2 loop filter c24 10uf c16 220nf c22 100pf l1 4.7nh c8 1nf c19 47pf c15 220nf c20 100pf +3v3_a rf in 950-2150mhz 75 ohms r22 33r r21 33r r13 47k r12 nf +3v3_a +3v3_a tp1 vlnbrf sk2 clk data sk1 c58 1pf qout 15 qoutb 16 vccbb 17 vccdig 26 ioutb 18 iout 19 sleep 20 scl 21 sda 22 xtal 25 xtalcap 24 vcccp 27 pump 28 vvar 1 p0 23 vccfe2 7 rfbypass 6 paddl e pad vccfe 1 8 nc 11 rf in 10 rf inb 12 nc 9 rf agc 14 vcclo 4 vccvco 3 lotest 5 nc 13 pad/ref 2 u3 CE5037
CE5037 data sheet 16 intel corporation 3.1 general design guidelines figure 4 shows a typical application using a ce6313 as a demodulator. this is available as a reference design (ce9542) from intel corporation. the design uses a standard two layer board. all com ponents are mounted on the upper surface with the lower surface as a ground plane. the rf input requires a coupli ng capacitor and series inductor for optimum matching. the rf bypass output requires a coupling capacitor. good decoupling should be used - these components should be mounted as close to the device as practicable. all ground contact to the CE5037 is to the ground ?paddle ? on the underside of the packa ge. this must be soldered fully to the board to achieve best thermal and electrical cont act. it is recommended that an array of vias (4 x 4) is used to achieve good contact to the ground plane underneath the device a common crystal reference can be used for the tuner and demodu lator. the crystal osc illator capacitors are optimised for a 10.111 mhz reference. sensitivity is optimised by minimizing interaction from digital signal activity in the demodulator. this is achieved by filtering in the agc control, and fi lter networks in the baseband i and q signals between the demodulator and CE5037. these networks should be mounted as close to the CE5037 as possible. the typical performance from the refer ence design is shown in the table below: further information is prov ided in ce9542 user guides. the CE5037 can also be used with other demodulators. if the demodulator has a single-ended input then the CE5037 can be used with a single-ended outputs ie iout and qout. the unused outputs should be loaded with an equivalent load to the demodulator input to mainta in a good balanced configuration. the optimum output level for the demodulator can be achieved by adjusting the post filter baseband gain. 3.2 dvb-s2 applications the excellent performance of the ce 5037 makes the device also suitable for the higher level modulation schemes (8psk) used for dvb-s2. in the critical areas of quadrat ure accuracy and phase noise, typical performance is shown in the following table. parameter typ. units notes sensitivity -83 dbm qef 27.5ms/s rate 7/8 no added noise c/n 27.5ms/s rate 7/8 2e-4 post viterbi ber 8.3 8.1 8.1 db db db input = -69 dbm -45 dbm -23 dbm c/n 2ms/s rate 7/8 2e-4 post viterbi ber 8.2 8.0 8.0 db db db input = -81dbm -45 dbm -23 dbm interference rejection ratio 27.5 ms/s rate 7/8. interferers at -25 dbm 32 35 45 35 db db db db n+1 n+4 n+10 2 interferers at -25dbm table 23 - typical performance using CE5037 and ce6313
CE5037 data sheet 17 intel corporation 3.3 baseband filter bandwidth calculation the bandwidth of the baseband filter is given by the following expression: equation 1 where: fbw = the filter bandwidth in mhz within the range 8 mhz to 43 mhz. fxtal = crystal oscilla tor frequenc y in mhz. br = decimal value of the bits br[4:0], range 1-31. (br = 0 is not allowed) bf = decimal value of the regist er bits bf[7:0], range 0 - 255. the above equation can be re-arranged as follows equation 2 it is recommended that br should be set so that is approximately 1 mhz this sets the bandwidth resolution to approximately 200khz the value of bf can now be calculated from equation 2 and rounded to the nearest integer: example conditions: fxtal = 10.111 mhz, fbw = 26.5 mhz choose br = 10 bf = 132 the actual filter bandwidt h is therefore given by: parameter value notes quadrature amplitude matching < 0.5 db filter bandwidth = 26.5 mhz quadrature phase matching < 2 integrated phase noise lo = 950mhz 0.40 rms pll loop bandwidth = 10khz phase noise integrated over 1khz to 10 mhz integrated phase noise lo = 1500mhz 0.62 rms integrated phase noise lo = 2150mhz 0.83 rms table 24 - typical performance for dvb-s2 applications () 1 bf x 5.088 x br fxtal fbw + = 1 fxtal br x 5.088 fbw x bf ? ? ? ? ? ? ? = br fxtal 132.35 1 10.111 10 x 5.088 x 26.5 bf = ? = () mhz 43 26 5.088 1 x 1 132 x 10 10.111 fbw . = + =
CE5037 data sheet 18 intel corporation 4.0 pin descriptions pin# name description schematic 1 vvar lo voltage tuning input. 2 pad/ref bonded to paddle. production continuity test for paddle soldering and also ground reference for loop filter. 3 vccvco +3.3 v voltage supply for vco's. 4 vcclo +3.3 v voltage supply for lo circuits. 5 lotest for intel testing only. must not connect. 6 rfbypass rf bypass output. ac couple. matching circuitry as shown in applications diagram. do not connect in applications where rf bypass is not required. 7 vccrf2 +3.3 v voltage supply for rf. 8 vccrf1 +3.3 v voltage supply for rf. 9 n/c not connected. 10 12 rfin rfin rf input. ac couple. see applications diagram. 11 n/c not connected. 13 n/c not connected. vvar 100 vbias components per vco vcc rfbypass rfin rfin
CE5037 data sheet 19 intel corporation 14 rfagc rf analog gain control input. 15 16 qout qout q channel baseband differential outputs. ac couple as shown in application diagram. 17 vccbb +3.3 v voltage supply for baseband. 18 19 iout iout i channel baseband differential outputs. ac couple as shown in application diagram. same as pin 15,16 20 sleep hardware power down input. logic '0' normal mode. logic '1' - analog sections are powered down including crystal oscillator. 21 scl i 2 c serial clock input pin# name description schematic rfagc vcc 10k 30k vref output vcc sleep cmos digital input scl cmos digital input
CE5037 data sheet 20 intel corporation 22 sda i 2 c serial data input/output 23 p0 switching port output. open drain '0' = disabled (high impedance) '1' = enabled. 24 25 xcap xtal reference oscillator crystal inputs. xtal pin can be used for external reference via 10nf capacitor. see applications diagram for recommended external components (10.111 mhz) 26 vccdig +3.3 v voltage supply for digital logic. 27 vcccp +3.3 v voltage supply for varactor tuning. 28 pump charge pump output. pin# name description schematic sda cmos digital input/output p0 cmos digital output xcap 0.2 ma xtal 100 vcc pump vcc
CE5037 data sheet 21 intel corporation 5.0 absolute maximum ratings 6.0 operating conditions parameter min. max. units notes maximum voltage on any vcc pin -0.3 3.6 v maximum voltage between any two vcc pins 0.3 v maximum voltage on any other pin -0.3 vcc + 0.3 v the voltage on any pin must not exceed 3.6 v maximum voltage between rfin and rfin -1 1 v p0 output current 20 ma maximum rf input 10 dbm storage temperature -55 150 c junction temperature 125 c package thermal resistance 34 c/w package ground paddle soldered to ground esd protection - all pins except 10,12 1.75 kv mil std 883b method 3015 cat1 esd protection - pins 10,12 rfin, rfin 0.75 kv mil std 883b method 3015 cat1 parameter min. max. units notes supply voltage 3.15 3.45 v operating temperature -10 +85 c rf input frequency 950 2150 mhz baseband i/q output load 4.7 15 k ? pf
CE5037 data sheet 22 intel corporation 7.0 electrical characteristics test conditions (unless otherwise stated) t amb = 25 o c, vee= 0v, all vcc supplies = 3.3 v+-5% baseband gain = 9 db, rfg = 0 baseband filter bandwidth 26.5 mhz all power levels are referred to 75 ? (0 dbm = 109 db v) specifications refer to total cascaded system of converter/agc stage and baseband amplifier/filter stage. output amplitude of 0.5 vp-p differential. characteristic min. typ. max. units conditions supply current 145 155 200 215 ma ma outputs unloaded. max filter bandwidth rf bypass disabled rf bypass enabled hardware power down software power down 0.2 1.7 3 ma ma no rf input. crystal oscillator remains operational system input return loss 9 db zo = 75 ? with external matching. bypass enabled or disabled noise figure dsb 8 8.5 10 10 13 db db db at max gain at -70 dbm operating level at -60 dbm operating level variation in nf with rf gain adjust -1 db/db above -60dbm operating level operating dynamic range -92 -10 dbm 1ms/s operating dynamic range -84 -10 dbm 27.5ms/s conversion gain max min 72 78 -6 10 db db rfagc = 0.2v rfagc = 2.8v agc control range 68 72 db agc monotonic for rfagc from vee to vcc rfagc input current -150 150 a vee <= rfagc<= vcc system im2 -28 -40 dbc dbc baseband defined, note 1 rf front-end defined, note 2 system im3 -24 -30 dbc dbc note 3 note 4 iip2 15 22 dbm at -40 dbm input, note 2 iip3 5 13 dbm at -25 dbm input, note 3
CE5037 data sheet 23 intel corporation lo second harmonic interference level -35 dbc note 5, all gain settings lna second harmonic interference level -20 dbc note 6 quadrature gain match -1 1 db 1.5 to 18 mhz quadrature phase match -3 -5 3 5 deg deg baseband signal = 1.5 mhz baseband signal = 18 mhz i & q channel in band ripple 1 db 1.5 to 18 mhz lo reference sideband spur level on i & q outputs -40 dbc synthesizer phase detector comparison frequency 500 - 2000 khz in band local oscillator leakage to rf input -65 -55 dbm dbm 950 - 2150 mhz 30 - 950 mhz channel lock time 50 ms worst case channels local oscillator vco gain 27 mhz/v lo = 2 ghz. note 7 ssb phase noise -83 -76 -96 -110 dbc/hz dbc/hz dbc/hz 10 khz offset 100 khz offset 1 mhz offset phase noise floor -132 dbc/hz integrated phase jitter 3 deg 10 khz to 15 mhz varactor input current -10 10 na vvar = 0.5 to 1.3 v baseband filters bandwidth 6 43 mhz max specified load bandwidth tolerance -1 +1 mhz all bandwidth settings time to change filter bandwidth 10 ms total harmonic distortion -30 dbc 1 vpp differential output at 43 mhz filter bandwidth rf bypass output load = 75 ohms gain -2 1.5 4 db noise figure 8.5 10 db opip3 9 db note 8 opip2 20 dbm note 9 output return loss 9 db forward isolation 30 db 950-2150 mhz. bypass disabled characteristic min. typ. max. units conditions
CE5037 data sheet 24 intel corporation reverse isolation 30 db 950-2150 mhz. bypass enabled or disabled in band lo leakage -65 dbm 950-2150 mhz. bypass enabled or disabled synthesizer charge pump current 304 422 578 762 400 550 750 1000 552 759 1035 1380 a a a a charge pump matching 2 % vpin = 0.5 to 1.3 v charge pump leakage -10 +/-3 +10 na vpin = 0.5 to 1.3 v charge pump compliance 0.4 vcc - 0.4 v crystal frequency 4 20 mhz recommended crystal series resistance 12 25 50 ohms 10 mhz crystal crystal power dissipation 100 500 w note 10 crystal load capacitance 16 pf note 10 crystal oscillator startup time 10 ms external reference input frequency 4 20 mhz ac coupled sinewave external reference drive level 0.5 2.0 vpp ac coupled sinewave phase detector comparison frequency 0.5 2 mhz equivalent phase noise at phase detector -148 dbc/hz 10 mhz crystal ssb within pll loop bandwidth interface sda, scl input high voltage input low voltage hysteresis input current 2.3 0 -10 0.4 3.6 1 10 v v a input = vee to vccdig +0.3 v sda output voltage 0.4 v isink = 3 ma scl clock rate 100 khz characteristic min. typ. max. units conditions
CE5037 data sheet 25 intel corporation note 1: agc set to deliver an output of 0.5vp-p with an input cw @ frequency fc of -30 dbm, undesired tones at fc+146 and fc+155 mhz @ -15 dbm, generating output im spur at 9 mhz. measured relative to unwanted signal. note 2: lo set to 2145 mhz and agc set to deliver a 5 mhz output of 0.5vp-p with an input cw @ frequency 2150 mhz of ?40 dbm. undesired tones at 1.05 and 1.1 ghz at -25 dbm generating im spur at 5 mhz baseband. measured relative to unwanted signal. note 3: agc set to deliver an output of 0.5vp-p with an input cw @ frequency fc of -30 dbm. two undesired tones at fc+205 and fc+405 mhz at -12 dbm, generating output im spur at 5 mhz. note 4: agc set to deliver an output of 0.5vp-p with an input cw @ frequency fc of -30 dbm. two undesired tones at fc+55 and fc+105 mhz at -15 dbm, generating output im spur at 5 mhz. note 5: the level of 2.01 ghz down co nverted to baseband relative to 1.01 ghz with the oscillator tu ned to 1 ghz. note 6: the level of second harmonic of 1.01 ghz at -20dbm downconverted to baseband relative to 2.01 ghz desired signal at -35dbm with agc set to give 0.5vp-p output. lo frequency = 2 ghz. note 7: reference vco gain value for loop f ilter calculations. using this recommended value then takes into account vco switchin g and automatic charge pump current variations. note 8: two input tones at fc+50 and fc+100 mhz at -12 dbm, generating output im product at fc. note 9: im2 product from two input tones at 1.05 and 1.1 ghz at -16 dbm, generating im product at 2150 mhz. note 10: crystal specifications vary considerab ly and significantly effect the choice of external oscillator capacitor values. e ach application may require separate consideration for optimum performance. external port p0 sink current leakage current 3 10 ma a vo = 0.7 v vo = vcc sleep input input high voltage input low voltage input current 1.9 vee 3.6 1.0 10 v v a vin = vee to vccdig characteristic min. typ. max. units conditions
CE5037 data sheet 26 intel corporation 8.0 typical performance data figure 5 - gain v. rfagc at 25c figure 6 - gain v rfagc v. temperature -10 0 10 20 30 40 50 60 70 80 00.511.522.53 agc voltage conversion gain db lo 950mhz lo 1550mhz lo 2150mhz -10 0 10 20 30 40 50 60 70 80 0 0.5 1 1.5 2 2.5 3 agc voltage conversion gain db -15c +25c +90c
CE5037 data sheet 27 intel corporation figure 7 - iip3 v gain at 25c figure 8 - iip2 v gain at 25c -50 -40 -30 -20 -10 0 10 20 20 30 40 50 60 70 80 gain setting db iip3 dbm 3.1vcc 3.3vcc 3.5vcc -30 -20 -10 0 10 20 30 35 40 45 50 55 60 65 70 75 gain setting db iip2 dbm 3.1vcc 3.3vcc 3.5vcc
CE5037 data sheet 28 intel corporation figure 9 - iip3 v gain at 25c (rfg = 1) figure 10 - iip2 v gain at 25c (rfg = 1 -40 -30 -20 -10 0 10 20 30 10 20 30 40 50 60 70 gain setting db iip3 dbm rfg set to -10db -20.0 -10.0 0.0 10.0 20.0 30.0 40.0 25 30 35 40 45 50 55 60 65 gain setting db iip2 dbm rfg set to -10db
CE5037 data sheet 29 intel corporation figure 11 - noise figure v freq at 25c figure 12 - noise figure v rfin v temperature rfin = -70dbm 6 7 8 9 10 11 12 950 1150 1350 1550 1750 1950 2150 frequency (mhz) nf (db) lo = 1550mhz 0 10 20 30 40 50 -80 -70 -60 -50 -40 -30 -20 -10 rfin (dbm) nf (db) -15c +25c +90c spec
CE5037 data sheet 30 intel corporation figure 13 - lo phase noise at 25c figure 14 - lo phase noise v temperature -130 -120 -110 -100 -90 -80 -70 10000 100000 1000000 1000000 0 frequency offset (hz) phase noise (dbc/hz) -120.0 -115.0 -110.0 -105.0 -100.0 -95.0 -90.0 -85.0 -80.0 1000 10000 100000 1000000 frequency offset (hz) phase noise (dbc/hz) -15degc +90degc
CE5037 data sheet 31 intel corporation figure 15 - rf bypass gain v temperature figure 16 - baseband filter response 26.5 mhz -4.0 -2.0 0.0 2.0 4.0 6.0 950 1150 1350 1550 1750 1950 2150 frequency (mhz) gain (db) -15c +25c +90c 26.5mhz filter response -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 04080120 baseband frequency (mhz) normalised amplitude (db) +90c +25c -15c

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